This invention relates to phase detectors and more particularly to a system and method for clock recovery from non-return-to-zero (NRZ) data and even more particularly to such a system and method for an improved timing margin half-rate continuous phase detector.
In data transmission systems using NRZ formatting, there is no explicit clock signal transmitted with the data that can be used to recover the data. The clock must first be recovered from the data, based on the time of the data transitions. This requires a phase detector which measures the phase error between the NRZ data and an internal clock, producing an error signal. The error signal drives a control loop that corrects the error. In a properly working system, the control loop will be able to hold the phase error to a negligible value. The recovered clock is then used to recover the data. A circuit which performs the above operations is called a clock/data recovery (CDR) circuit. Nearly all modern data transmission systems use CDR circuits and the phase detector is an essential part of such a CDR circuit.
Two classes of phase detectors are in common use, commonly referred to as xe2x80x9cbang-bangxe2x80x9d and xe2x80x9ccontinuous.xe2x80x9d The bang-bang circuits are derived from Alexander""s original design, as discussed in Alexander, J D H, xe2x80x9cClock Recovery from Random Binary Signals,xe2x80x9d Electronic Letters, v. 11, n. 32, pp 541-542, Oct. 30, 1975. The bang-bang class has a binary quantized output that only indicates whether the clock is xe2x80x9cearlyxe2x80x9d or xe2x80x9clate,xe2x80x9d but not by how much. This results in the control loop operating in a discontinuous or xe2x80x9cbang-bangxe2x80x9d mode, which adds spurious jitter to the recovered clock and thus argues against the use of bang-bang phase detectors in jitter measurement systems. Also, in communications systems, this spurious jitter reduces the performance of the system.
The continuous phase detectors are patterned after, or emulate, Hogge""s original design as discussed in Hogge, C P, xe2x80x9cA Self Correcting Clock Recovery Circuit,xe2x80x9d Journal of Lightwave Technology, v. LT-3, n. 6, pp 1312-1314, December 1985. These detectors have an output that can be used to generate a voltage proportional to phase error, thus resulting in a xe2x80x9cproportionalxe2x80x9d mode for the control loop. This is much more desirable in operational systems and essential in jitter measurement systems. However, many systems operating at state-of-the-art clock rates still use bang-bang phase detectors because they will operate considerably faster than continuous phase detectors, for a given logic hardware technology. This is because the timing is more critical in the continuous phase detectors of known design.
The phase detectors described above are clocked at xe2x80x9cfull rate,xe2x80x9d meaning that the clock frequency is equal to the baud rate of the data. For example, if the data is at a 10 Gbit/s rate (1010 baud), and the clock is 10 GHz, the circuit is described as being clocked at xe2x80x9cfull rate.xe2x80x9d In this context, xe2x80x9chalf ratexe2x80x9d clocking would refer, for example, to 10 Gbit/s data with a 5 GHz clock.
In an effort to get more speed, xe2x80x9chalf-ratexe2x80x9d clocked continuous phase detectors have been developed as discussed by Reis, A D, et al, xe2x80x9cHigh Date Rate Synchronizers Operating at Low Speed.xe2x80x9d KEGS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems, 2001, pp 1127-1130, V3 and Savoj, J and Razavi, B, xe2x80x9cDesign of Half-Rate Clock and Data Recovery Circuits for Optical Communications Systems, IEEE Journal of Solid-State Circuits, V36, No, 5, May 2001, pp 761-768. The clock has two phases, 180xc2x0 apart, which activate duplicate flip-flops. The 2 phases correspond to the rising and falling edges of the clock waveform. This modification, potentially at least, gives the flip-flops twice as much time to switch, and thus enables up to twice the maximum clock rate. However, these half-rate phase detectors still have limitations with respect to critical timing margins that limit their maximum clock rate. It should also be noted, that because of the analog nature of continuous phase detectors, their accuracy and dynamic range gradually deteriorate as the maximum rate is approached. Therefore, even below the maximum rate, increased design margin usually improves performance. These increased margins then effectively increase the maximum data rate. Accordingly, a need exists in the art for a half-rate continuous phase detector with improved timing margins for increased speed and performance.
The present invention is directed to a phase detector constructed from a plurality of multi-input gates which combine combinations of unretimed input data with retimed data and with clock signals to achieve output pulses proportional to the phase difference between the unretimed data and the clock.
In the embodiment the phase detector comprises an input for receiving data signals; an input for receiving clock signals; an output for providing phase control signals; data retiming circuiting for accepting unretimed data signals from said data input and for providing even and odd retimed signals therefrom; a plurality of multi-input gates having inputs connected to different combinations of said unretimed data signals, said retimed data signals, and said clock signals, such that no said gate can be active in two consecutive UIs, when a UI is defined as the length of time allocated to a single bit; and a combiner for mixing the outputs of at least two of said gates.
The forgoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart form the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended. as a definition of the limits of the present invention.